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TV-Stereo Processor
TDA 6610-5
Bipolar IC
Features
q AII functions are I2C Bus controlled q Suitable for multistandard including NICAM SCART-
interface
q Independent headphones output high signal noise ratio q Extremely low total harmonic distortion q High security of detection of the stereo decoder part
because of the digital interference suppression and the very narrow bandwidth
P-DIP-28-3
Type TDA 6610-5
Ordering Code Q67000-A5126
Package P-DIP-28-3
General The TDA 6610-5 represents a complete TV-stereo sound system controlled via the I2C Bus. The IC is divided into three functional blocks: 1. Stereo Sound Processing with High Quality (exceeds DIN 45500; suitable for NICAM and CD) a) Matrix for G-standard b) Additional single-channel AF-input (for e.g. AF-signal according to L-standard) c) Stereo SCART-interface is in accordance with FTZ-official specification d) Stereo loudspeaker signal section with Ch1/Ch2 switch, treble/bass control, quasi-stereo/ stereo base width control and separate left/right loudspeaker volume control e) Signal section with Ch1/Ch2 switch and volume control for stereo headphones
39
06.94
TDA 6610-5
2. TV-Sound Identification Signal Decoder Consisting of: a) Active pilot signal filter b) Phase-independent rectifier with very narrow bandwidth for evaluation of the identification signal c) Digital integrator to reduce interference d) Multiplexer for cyclical switch over between "stereo" or "dual" recognition e) PLL for the generation of the reference signal. External synchronization with either the flyback pulse or external reference clock signals of 62.5 kHz 3. Control Section for: a) I2C Bus interface with listen/talk function b) Control of the complete AF-sound processing c) Control of the identification signal decoder d) Reading of the identification signal decoder status e) Test modes
Semiconductor Group
40
TDA 6610-5
Pin Functions Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Function AF-input mono, left, sound 1 Bias for AF-unit AF-input right, sound 2 54-kHz input 54-kHz filter AF-input (L-standard) AF-input SCART left (sound 1) AF-input SCART right (sound 2) AF-output SCART (mono, sound 1, left) AF-output SCART (mono, sound 2, right) Phase-shifter quasi-stereo Phase-shifter quasi-stereo Cut-off frequency base (base-width) left Cut-off frequency base (base-width) right AF-output, loudspeaker left AF-output, loudspeaker right Cut-off frequency treble left Cut-off frequency treble right AF-output, headphones left AF-output, headphones right + VS (supply voltage) I2C Bus SCL I2C Bus SDA Input H-pulse (4 x H-pulse) Filter ID-signal decoder Filter ID-signal decoder PLL-filter ID-signal decoder Ground
Semiconductor Group
41
TDA 6610-5
Block Diagram Semiconductor Group 42
TDA 6610-5
Circuit Description Signal Section The audio signal processing in the matrix and the switch-over for multichannel TV-sound signals according to the two-carrier system used in Germany takes place in the matrix and switching sections. In addition to the two inputs for the demodulated sound carrier a two-channel SCARTinput and an additional mono input (e.g. for demodulated L-standard sound) are provided. The two AF-inputs can be by-passed internally in such a way that decoded stereo sound signals of other audio systems (NICAM) can be processed. The switching section is terminated with the SCARToutput and an independently switchable Ch1/Ch2 switch for the loudspeaker and headphone outputs. In the loudspeaker signal path a switchable quasi-stereo section follows the Ch1/Ch2 switch. This section gives a special audio effect with mono signals due to a 180 phase shift at medium frequencies (about 1 kHz) in one channel. The following bass control exhibits a step of 3 dB with an adjustment range of + 15/- 12 dB. The cutoff frequency is set for each channel with an external capacitor. A circuit for stereo base-width expansion, switchable if stereo signals are recognized, provides a more spatial audio effect due to 50 % of frequency dependent crosstalk in opposing phases. The circuit operates with the same cut-off frequency as the bass control, but the function is largely independent. Likewise the treble control, whose cut-off frequency is also controlled by a capacitor in each channel, has a step of 3 dB with an adjustment range of 12 dB. The volume control can be adjusted independently for the right and left loudspeaker signal path. Using 57 steps of 1.25 dB each, a 70 dB adjustment range is available, where the 57th step activates the "MUTE" function. Functions such as "balance" or "loudness" are realized by software adjustment of the appropriate tone and volume controls. In the signal path for the headphones after the Ch1/Ch2 switch a volume control circuit is used for the simultaneous left/right adjustment. Thirty-two steps of 2 dB each allow an adjustment range of 62 dB (31 x 2 dB = 62 dB, while the 32nd step activates the "MUTE" function). Identification Sound Decoder The input of the identification sound decoder consists of an op-amp for the pilot signal with its sidebands. An external LC-circuit is used to select the pilot carrier and his sidebands. The signal is then passed to a phase-independent active band-pass filter wih a very narrow bandwidth (adjustable externally). This filter detects whether the lower side-band of the pilot carrier, modulated with the identification signal, is present. The center frequency of the filter is switched between "dual" and "stereo" by a multiplexer. The multiplexing frequency is adjustable by software. If a side-band is detected, the multiplexer stops. The first "detected" criterion is processed by a digital integrator and a following comparator in order to suppress interferences due to noise. The decoder status caw can be read out via I 2 C Bus (talk mode) as the "stereo" or "dual" mode. The control of the corresponding signal path can take place either directly internally or through the C . All required clock signals are derived from a fast lowding PLL synchronized by a external reference frequency. This reference frequency has to be sufficiently close to the horizontal frequency, but a rigid phase coupling is not required. Therefore, alternatively to the line frequency the use of a crystalcontrolled 62.5 kHz frequency commonly available in PLL-tuning systems is possible.
Semiconductor Group
43
TDA 6610-5
Control Section All functions are controlled via I2C Bus interface with listen/talk functions. The actual valid data are stored in a latch block. The telegram structure is: start condition - chip address - any number of data bytes - stop condition The following conditions apply to the data bytes: Before a data byte (with the adjustment information) is transmitted, a subaddress byte has always to be transmitted. Example: The headphone volume (HP vol) has to be increased in several (i.e. 3) steps.
Right Start condition Chip address Subaddr. vol Volume step 8 Subaddr. vol Volume step 9 Subaddr. vol Volume step 10 Stop condition 84 (Hex) 03 (Hex) 08 (Hex) 03 (Hex) 09 (Hex) 03 (Hex) 0A (Hex)
Wrong Start condition Chip address Subaddr. vol Volume step 8 Volume step 9 Volume step 10 Stop condition 84 (Hex) 03 (Hex) 08 (Hex) 09 (Hex) 0A (Hex)
Within a telegram (i.e. without a new start condition) any different subaddresses can be accessed. The changeover between "listen" and "talk" however has always to be initialized via the sequence "stop condition - start condition - chip address". Before each readout always a start condition and chip address (talk) has to be transmitted. The data to be read out are loaded into the I2C Bus interface after this sequence and are available for the transfer to the C. Chip Address MSB 1 * 0 * 0 * 0 * 0 * 1 * 0 LSB R/W
R/W = 0 Read (Listen) R/W = 1 Write (Talk)
Semiconductor Group
44
TDA 6610-5
Subaddress Bytes MSB Loudspeaker volume left Loudspeaker volume right Headphone volume Treble/bass Switch byte I Switch byte II X X X X X X * X X X X X X * X X X X X X * X X X X X X * X X X X X X * 0 0 0 1 1 0 * 0 1 1 0 1 0 LSB 1 0 1 1 1 0
Setting Bytes a) Loudspeaker Volume Left / Right MSB Maximum volume Max - 1 step Max - 15 steps Max - 55 steps MUTE MUTE MUTE Power ON b) Headphone Volume MSB Max. volume Max - 1 step Max - 15 steps Max - 31 steps MUTE Power ON T2 T2 T2 T2 T2 0 * T1 T1 T1 T1 T1 0 * T0 T0 T0 T0 T0 0 * 1 1 1 0 0 0 * 1 1 0 0 0 0 * 1 1 0 0 0 0 * 1 1 0 0 0 0 LSB 1 0 0 1 0 1 X X X X X X X 0 * X X X X X X X 0 * 1 1 1 0 0 0 0 0 * 1 1 1 0 0 0 0 0 * 1 1 0 1 0 0 0 0 * 1 1 0 0 1 0 X 0 * 1 1 0 0 1 0 X 0 LSB 1 0 0 0 1 0 X 1
T0 - T2 are test bits; these have to be set to 0 for normal operation.
Semiconductor Group
45
TDA 6610-5
c) Treble / Bass MSB Linear Max. treble, lin. bass Max. treble, lin. bass Min. treble, lin. bass Min. treble, lin. bass Lin. treble, max. bass Lin. treble, max. bass Lin. treble, max. bass Lin. treble, min. bass Lin. treble, min. bass Max. treble, max. bass Min. treble, min. bass Power ON 1 1 1 0 0 1 1 1 1 1 1 0 0 MSB treble * 0 1 1 1 0 0 0 0 0 0 1 0 0 * 0 0 X 0 X 0 0 0 0 0 X X 0 * 0 0 X 0 X 0 0 0 0 0 X X 0 LSB treble * 1 1 1 1 1 1 1 1 0 0 1 0 0 MSB bass * 0 0 0 0 0 1 1 1 1 0 1 0 0 * 0 0 0 0 0 0 X 1 0 X X X 0 LSB 0 0 0 0 0 1 1 X 0 X 1 X 1 LSB bass
Semiconductor Group
46
TDA 6610-5
d) Switch Byte I MSB MUTE I * MUTE II * Ch1/Ch2vol * Ch1/Ch2HP * Mono * SCART * SCART-D LSB AM
MUTE I =0 All AF-outputs are muted (loudspeakers, headphones, SCART); power ON MUTE I =1 All AF-outputs ON MUTE II = 0 Loudspeaker outputs muted; power ON MUTE II = 1 Loudspeaker outputs ON MUTE I and MUTE II are OR gated with respect to the loudspeaker outputs MUTE I 0 0 1 1 MUTE II 0 1 0 1 Loudspeaker outputs muted muted muted ON Headphones, SCART-outputs muted muted ON ON
CH1/Ch2vol = 0 Sound 1 on the loudspeaker outputs; power ON CH1/Ch2vol = 1 Sound 2 on the loudspeaker outputs Sound 1 on the headphone outputs; power ON CH1/Ch2HP = 0 CH1/Ch2HP = 1 Sound 2 on the headphone outputs CH1/Ch2vol and CH1/Ch2HP are only effective if the matrix is set to the position "dual sound". Mono Mono SCART SCART SCART-D SCART-D Standard L Standard L = = = = = = = = 0 1 0 1 0 1 0 1 identification signal decoder is set to mono position and held; power ON normal operation of identification signal decoder normal TV-operation; power ON SCART-playback; connection of SCART-inputs - AF-outputs. SCART = 1 has priority over AM = 1 (loudspeaker and headphones) SCART-playback stereo (mono); power ON Enable for the Ch1/Ch2 switch during SCART-playback (only effective when SCART = 1) normal operation (G-standard) AM AF-input is activated; power ON AM = 1 has priority over bypass = 1
Semiconductor Group
47
TDA 6610-5
e) Switch Byte II MSB MPX0 MPX0 0 0 1 * MPX1 MPX 1 0 1 0 * Quasi-st MPX period 2s 4s 8s * Be * H-pul * Matrix 0 * Matrix 1 LSB Bypass
power ON
recommended C25, 26 1 F 2.2 F 4.7 F
MPX-period = 2 s signifies: Identification (ID) signal decoder searches 1 s for dual and 1 s for stereo transmission Quasi-st Quasi-St Be Be H pul H pul Matrix 0 0 0 1 1 Bypass Bypass = = = = = = = = 0 1 0 1 0 1 Quasi-stereo OFF; Power ON Quasi-stereo ON Stereo basewidth expansion OFF; Power ON Stereo basewidth expansion ON ID-signal decoder synchronization with f H = 15.625 kHz; power ON ID-synchronization with 4 x f H Matrix status mono power ON stereo dual automatic according to ID-signal decoder Normal operations (G-standard) Matrix is bridged so that left/right signals can be fed in; power ON (AM = 1 has priority over bypass = 1)
Matrix 1 0 1 0 1 0 1
Semiconductor Group
48
TDA 6610-5
Priority List of Setting Bits 1. 2. 3. 4. 5. 6. MUTE I MUTE II (only with regard to the loudspeaker outputs) SCART Standard L Bypass Matrix 0, 1
h) Talk Mode MS St 0 1 0 1 * D 0 0 1 1 * T5 * T4 * T3 * X * X LSB X
decoder detects mono decoder detects stereo decoder detects dual internally inhibited
T3 - T5 are test bits
Semiconductor Group
49
TDA 6610-5
Absolute Maximum Ratings TA = 0 to 70 oC; all voltages relatives to VSS Parameter Supply voltage Max. DC-voltage Max. DC-voltage Max. DC-voltage Max. DC-voltage Max. DC-voltage Max. DC-voltage Max. DC-voltage Max. DC-voltage Max. DC-voltage Max. DC-voltage Max. DC-voltage Max. DC-voltage Max. DC-voltage Max. DC-voltage Max. DC-voltage Max. DC-voltage Max. DC-voltage Max. DC-voltage Max. DC-current Max. DC-current Max. DC-current Max. DC-current Max. DC-current Max. DC-current Max. DC-current Max. DC-current Junction temperature Storage temperature Thermal resistance system ambient Operating Range Supply voltage Ambient temperature Input frequency range Symbol min. Limit Values max. 14 V V V V V V V V V V V V V V V V V V V mA mA mA mA mA mA mA mA
oC oC
Unit
V21 V1 V2 V3 V4 V6 V7 V8 V11 V12 V13 V14 V17 V18 V22 V23 V24 V25 V26 I5 I9 I10 I15 I16 I19 I20 I27 Tj Tstg Rth SA
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 - 40
V21 V21 V21 V21 V21 V21 V21 V21 V21 V21 V21 V21 V21 V21 V21 V21 V21 V21
2 2 2 2 2 2 2 1 150 125 53
K/W
V6 TA fI
10 0 0.01
13.2 70 20
V
oC
kHz
Semiconductor Group
50
TDA 6610-5
Characteristics
VS = 12 V; TA = 25 oC, in accordance with test circuit 1
I2C Bus present: start - 84 - 01,3F - 0 2,3F - 0 3,1F - 0 5,88 - 0 6,10 - 07,C8 - 00,01 - stop Chip address - Vol LSl 63 - Vol LSr 63 - Vol HP 31 - tone lin - adj 0dB - MUTE I, MUTE II, Mono Bypass The basic setting for each point in the specification is always preset; only settings which deviate from this are given in the test conditions. Details in italics only provide explanation of the hexadecimal code and with switch bits on the set bits and features are stated.
Parameter
Symbol
Limit Values min. typ. 50 max.
Unit mA
Test Condition
Current consumption I21 Signal Section Max. gain Max. gain Max. gain Max. gain Max. gain Max. gain Max. gain Max. gain Max. gain Max. gain Max. gain Max. gain Max. gain Max. gain Max. gain Max. gain Max. gain Max. gain
V16-1 V15-3 V20-1 V19-3 V16-3 V15-3 V20-3 V19-3 V16-1 V20-1 V16-7 V15-8 V20-7 V19-8 V16-6 V15-6 V20-6 V19-6
-2 -2 -2 -2 -2 -2 -2 -2 4 4 -5 -5 -5 -5 -2 -2 -2 -2
0 0 0 0 0 0 0 0 6 6 -3 -3 -3 -3 0 0 0 0
2 2 2 2 2 2 2 2 8 8 -1 -1 -1 -1 2 2 2 2
dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB
00,02; V1 = 01 Matrix: Stereo 00,02; V1 = 01 Matrix: Stereo 00,02; V1 = 0 Matrix: Stereo 00,02; V1 = 0 Matrix: Stereo 00,02; V3 = 0 Matrix: Stereo 00,02; V3 = 0 Matrix: Stereo 07,CC, SCART 07,CC, SCART 07,CC, SCART 07,CC, SCART 07,C9, Standard L 07,C9, Standard L 07,C9, Standard L 07,C9, Standard L
Semiconductor Group
51
TDA 6610-5
Characteristics (cont'd) VS = 12 V; TA = 25 oC, in accordance with test circuit 1 Parameter Gain Gain Gain Gain Gain Gain Gain Min. gain Min. gain Symbol Limit Values min. typ. 0 0 0 0 6 0 0 - 70 - 70 max. 2 2 2 2 8 2 2 dB dB dB dB dB dB dB dB dB -2 -2 -2 -2 4 -2 -2 - 65 - 65 Unit Test Condition
V9-1 V10-3 V9-3 V10-3 V9-1 V10-6 V9-6 V16-1 V15-3 V20-1 V19-3 V16-7 V15-8 V20-7 V19-8 V16-6 V15-6 V20-6 V19-6
V15-16 V19-20
00,02; V1 = 0 Matrix: Stereo 00,02; V1 = 0 Matrix: Stereo 00,02; V3 = 0 Matrix: Stereo 07,C9 Standard L 07,C9 Standard L 01,08-02,08 Vol LSl 8-Vol LSr 8 01,08-02,08 Vol LSl 8-Vol LSr 8 01,08-02,08 03,01Vol HP 1 03,01Vol HP 1 07,CC-01,08-02,08 SCART-Vol LSl 8-Vol LSr 8 07,CC-01,08-02,08 SCART-Vol LSl 8-VolLSr 8 07,CC-03,01 SCART-Vol KH 1 07,CC-03,01 SCART-Vol KH 1 07,C9-01,08-02,08 Standard L Vol LSl 8-Vol LSr 8 07,C9-01,08-02,08 Standard L Vol LSl 8-Vol LSr 8 07,C9-03,01 Standard L Vol KH 1 07,C9-03,01 Standard L Vol KH 1 01,3F to 01,24 02,3F to 02,24 Vol LSl 63-36-Vol LSr 63-36 03,1F to 03,13 Vol KH 31-19
Min. gain Min. gain Min. gain Min. gain Min. gain Min. gain Min. gain Min. gain Min. gain Min. gain Flutter and wow
- 57 - 57 - 68 - 68 - 60 - 60 - 60 - 60 - 57 - 57
- 62 - 62 - 73 - 73 - 65 - 65 - 70 - 70 - 62 - 62 2 2
dB dB dB dB dB dB dB dB dB dB dB
Flutter and wow
dB
Semiconductor Group
52
TDA 6610-5
Characteristics (cont'd) VS = 12 V; TA = 25 oC, in accordance with test circuit 1 Parameter Step width Vol15 Step width Vol16 Step width Vol19 Step width Vol20 Bass boost Bass boost Bass boost Bass boost Step wide bass Step wide bass High frequency emphasis High frequency emphasis High frequency emphasis High frequency emphasis Step wide treble Step wide treble Linearity sound Linearity sound Channel separation Channel separation Channel separation Symbol V15 V16 V19 V20 0 0 0 0 13 13 - 10 - 10 1 1 10 10 - 10 - 10 1 1 Limit Values min. typ. 1.25 1.25 2 2 15 15 - 12 - 12 3 3 12 12 - 12 - 12 3 3 5 5 2 2 50 50 50 5 5 max. 2.5 2.5 4 4 dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB 01,X-01, (X 1) Vol LSl X-Vol LSl (X 02,X-02,(X1) Vol Lsr X-Vol LSr (X 03,X-03, (X 1) Vol KH X-Vol KH (X 03,X-03, (X 1) Vol KH X-Vol KH (X 05,8F; fI = 40 Hz Bass max, treble lin. 05,8F; fI = 40 Hz Bass max, treble lin. 05,8F; fI = 40 Hz Bass max, treble lin. 05,8F; fI = 40 Hz Bass max, treble lin. 05,8X-05,8 (X 1) Bass X - bass (X 1) 05,8X-05,8 (X 1) Bass X - bass (X 1) 05,8F; f l = 15 kHz Treble max, bass lin. 05,8F; f l = 15 kHz Treble max, bass lin. 05,8F; f Il = 15 kHz Treble max, bass lin. 05,8F; fl = 15 kHz Treble max, bass lin. 05,X8-0,5 (X 1) 8 Treble X - treble (X 1) 05,X8-0,5 (X 1) 8 Treble X - treble (X 1) 05,88; f l = 40 Hz - 15 kHz Treble, bass lin. 05,88; f l = 40 Hz - 15 kHz Treble, bass lin. Unit Test Condition
1) 1) 1) 1)
V16-1 V15-3 V16-1 V15-3
V15 V16
V16-1 V15-3 V16-1 V15-3
V15 V16 V15 V16 V15-16 V19-20 V9-10
V3 or V1 = 600 mVrms V3 or V1 = 600 mVrms V3 or V1 = 600 mVrms
Semiconductor Group
53
TDA 6610-5
Characteristics (cont'd) VS = 12 V; TA = 25 oC, in accordance with test circuit 1 Parameter Cross talk attenuation switch Symbol input interf
/ Output rms
Limit Values min. typ. max.
Unit
Test Condition
60 Attenuation MUTE 1-16 1-16 1-16 3-15 3-15 3-15 1-20 1-20 3-19 3-19 80
dB dB
Vl rms = 0 Vl Int1,3,6 = 600 mVrms Vl Int7,8 = 2 Vrms 01,00-02,00 Vol LSl 0-Vol LSr 0 V1 = 600 mVrms 07,48; V1 = 600 mVrms MUTE I: 0 07,88; V1 = 600 mVrms MUTE II: 0 01,00-02,00 Vol LSl 0-Vol LSr 0 V3 = 600 mVrms 07,48; V3 = 600 mVrms MUTE I: 0 07,88; V3 = 600 mVrms MUTE II: 0 03,00; V1 = 600 mVrms Vol KH 0 07,48; V1 = 600 mVrms MUTE I: 0 03,00; V3 = 600 mVrms Vol KH 0 07,48; V3 = 600 mVrms MUTE I: 0 07,48; V3 = 600 mVrms MUTE I: 0 07,48; V3 = 600 mVrms MUTE I: 0 07,49; V6 = 600 mVrms MUTE I: 0, Standard L 07,49; V6 = 600 mVrms MUTE I: 0, Standard L
Attenuation MUTE Attenuation MUTE Attenuation MUTE
80 80 80
dB dB dB
Attenuation MUTE Attenuation MUTE Attenuation MUTE Attenuation MUTE Attenuation MUTE Attenuation MUTE
80 80 80 80 80 80
dB dB dB dB dB dB
Analog values are valid for feed-in at the pin 6, 7, 8; V7, 8 = 2 Vrms; V6 = 600 mVrms Attenuation MUTE Attenuation MUTE Attenuation MUTE Attenuation MUTE 3-10 1-9 6-10 6-9 80 80 80 80 dB dB dB dB
Semiconductor Group
54
TDA 6610-5
Characteristics (cont'd) VS = 12 V; TA = 25 oC, in accordance with test circuit 1 Parameter Max. input voltage Max. input voltage Max. input voltage Max. input voltage Max. input voltage Max. input voltage Distortion Distortion Distortion Distortion Symbol Limit Values min. typ. max. mVrms mVrms mVrms mVrms Vrms Vrms % 0.01 0.01 0.01 0.01 0.1 0.1 0.1 0.1 % % % % 600 600 600 300 2 2 0 Unit Test Condition
V6 V3 V1 V1 V7 V8 THD19 THD20 THD19 THD20
THD15,16 = 1 % THD15 = 1 % THD16 = 1 % THD16 = 1 %; 00,02
Matrix: Stereo THD16 = 1 % 07, CC, SCART THD15 = 3 % 07, CC, SCART
V3 = 250 mVrms V1 = 250 mVrms V3 = 250 mVrms; 03,15
VolKH 21 V1 = 250 mVrms; 03,15 VolKH 21
Analog values are valid for feed-in at the pin 6, 7, 8; V7,8 = 2 Vrms; V6 = 250 mVrms Distortion Distortion Distortion
THD16 THD15 THD16 THD15 THD16 THD15
0.01 0.01 0.01
0.1 0.1 0.2
% % %
V1 = 250 mVrms V3 = 250 mVrms V1 = 250 mVrms; 01
2F-02,2F Vol LSl 47-Vol LSr 47 V3 = 250 mVrms; 01 2F-02,2F Vol LSl 47-Vol LSr 47 V1 = 250 mVrms; 05,XX any sound V3 = 250 mVrms; 05,XX any sound
Distortion
0.01
0.2
%
Distortion Distortion
0.01 0.01
0.4 0.4
% %
Analog values are valid for feed-in at the pin 6, 7, 8; V7,8 = 2 Vrms; V6 = 250 mVrms Distortion Distortion Distortion Distortion Antiphase Cross talk atten. Base width
THD10 THD9 THD10 THD9
V16-15 0.5
0.01 0.01 0.01 0.01 0.55
0.1 0.1 0.1 0.1
% % % %
V3 = 250 mVrms V1 = 250 mVrms V6 = 250 mVrms
07,C9, Standard L V1 = 250 mVrms 07,C9, Standard L
V3 = 600 mVrms fl = 2 kHz; 00,11, Basis width
Semiconductor Group
55
TDA 6610-5
Characteristics (cont'd) VS = 12 V; TA = 25 oC, in accordance with test circuit 1 Parameter Antiphase Cross talk atten. Base width Base width phase Base width phase Phase rotation quasi stereo Phase rotation quasi stereo Phase rotation quasi stereo Unweighted signalto-noise ratio Unweighted signalto-noise ratio Unweighted signalto-noise ratio 16-15 15-16 16-15 16-15 16-15 S / N16 S / N15 S / N16 150 150 0 130 - 30 1 1 70 180 180 10 180 10 90 90 80 210 210 40 230 0 97 97 deg deg deg deg deg dB dB dB Symbol V16-15 0.5 Limit Values min. typ. 0.55 max. Unit Test Condition
V3 = 600 mVrms fl = 2 kHz; 00,11, Basis width V1 = 600 mVrms; 00,11 Basis width, f = 2 kHz V1 = 600 mVrms; 00,11 Basis width, f = 2 kHz V3,1 = 600 mVrms; 00,21 Quasi stereo, f = 40 Hz V3,1 = 600 mVrms; 00,21 Quasi stereo, f = 1 kHz V3,1 = 600 mVrms; 00,21 Quasi stereo, f = 15 kHz
VN rms 20 Hz-20 kHz ; V1 = 0.6 Vrms VN rms 20 Hz-20 kHz ; V3 = 0.6 Vrms VN rms 20 Hz-20 kHz ; V1 = 0.6 Vrms 01,27-02,27 Vol LSl 39-Vol LSr 39 VN rms 20 Hz-20 kHz ; V3 = 0.6 Vrms 01,27-02,27 Vol LSl 39-Vol LSr 39 VN rms 20 Hz-20 kHz 01,00-02,00 Vol LSl 0-Vol LSr 0 VN rms 20 Hz-20 kHz 01,00-02,00 Vol LSl 0-Vol LSr 0
Unweighted signalto-noise ratio
S / N15
70
80
dB
External voltage
VN15 VN16
2
10
Vrms Vrms
External voltage
2
10
Semiconductor Group
56
TDA 6610-5
Characteristics (cont'd) VS = 12 V; TA = 25 oC, in accordance with test circuit 1 Parameter Unweighted signalto-noise ratio Unweighted signalto-noise ratio Unweighted signalto-noise ratio Unweighted signalto-noise ratio External voltage External voltage Unweighted signalto-noise ratio Unweighted signalto-noise ratio Change of DC-switch 1 Bit Change of DC-switch 1 Bit Change of DC-switch 1 Bit Change of DC-switch 1 Bit Change of DC-switch 1 Bit Change of DC-switch 1 Bit Symbol S / N20 S / N19 S / N20 S / N19 90 1 70 Limit Values min. typ. 97 90 80 97 max. dB dB dB VN rms 20 Hz-20 kHz ; V1 = 0.6 Vrms VN rms 20 Hz-20 kHz ; V3 = 0.6 Vrms VN rms 20 Hz-20 kHz ; V1 = 0.6 Vrms 03,10, Vol KH 16 VN rms 20 Hz-20 kHz ; V3 = 0.6 Vrms 03,10, Vol KH 16 VN rms 20 Hz-20 kHz ; 03,00 Vol KH 0 VN rms 20 Hz-20 kHz ; 03,00 Vol KH 0 VN rms 20 Hz-20 kHz ; V1 = 0.6 Vrms VN rms 20 Hz-20 kHz ; V1 = 0.6 Vrms 01,X-01,X 1 Vol LSl X-Vol LSl (X 1) 02,X-02,X 1 Vol LSr X-Vol LSr (X 1) 05,X-05,X 1 Sound X-Sound (X 1) 05,X-05,X 1 Sound X-Sound (X 1) 03,X-03,X 1 Vol KHX-Vol KH (X 1) 03,X-03,X 1 Vol KHX-Vol KH (X 1) Unit Test Condition
70
80
dB
VN20 VN19
S / N9 S / N10 V16 V15 V16 V15 V19 V20 1 1
2 2 90 90
10 10 97 97 10 10 10 10 10 10
Vrms Vrms dB dB mV mV mV mV mV mV
Semiconductor Group
57
TDA 6610-5
Characteristics (cont'd) VS = 12 V; TA = 25 oC, in accordance with test circuit 1 Parameter Symbol Limit Values min. Design-Related Data Input resistance Input resistance Input resistance Input resistance Input resistance Output resistance Output resistance Output resistance Output resistance Output resistance Output resistance typ. max. Unit Test Condition
R7 R8 R6 R3 R1 R 19 R 20 R 15 R 16 R9 R 10
35 35 20 20 20 200 200 200 200 200 200
k k k k k
Semiconductor Group
58
TDA 6610-5
Characteristics (cont'd) VS = 12 V; TA = 25 oC Parameter Symbol Limit Values min. ID-Signal Decoder Gain Filter OP-amp Max. input voltage VCO voltage PLL VCO voltage PLL VCO voltage PLL VCO voltage PLL typ. max. Unit Test Condition Test Circuit
V5 V5 V27 V27 V27 V27 V27
13 600 1.3 2
14
15
dB V
VIF = 80 mVpp f 24 = 14.6 kHz; V24 = 2.5 V f 24 = 15.625 kHz; V24 = 2.5 V f 24 = 16.6 kHz; V24 = 2.5 V f 24 = 58.4 kHz; V24 = 2.5 V
00,09, H-Imp
1 2 2 2 2
mVpp Function
3
4 4.7
V V V
1.3
2
VCO voltage PLL
4.7
V
f 24 = 66.4 kHz; V24 = 2.5 V
00,09, H-Imp 2
V KT FILTER
( V 25 - V 25 * ) 2 + ( V 26 - V 26 * ) = --------------------------------------------------------------------------------- V25 or V26 when V5 = 0 V5 V25* or V26* when V5 = 400 mVpp
VKT Filter VKT Filter
3.4 3.4 6.8 6.8
f 5 = Pilot signal: dual I2C-talk: dual f 5 = Pilot signal: stereo I2C-talk: stereo
2
ID-filter gain ID-filter gain
V25 test = V25 (V5 = 0) V25 ; V26 test = V26 (V5 = 0) V26
Detection threshold Detection threshold Detection threshold Detection threshold V25 - V25 V26 - V26 900 900 900 900 mV mV mV mV I2C-talk: stereo or dual I2C-talk: stereo or dual I2C-talk: stereo or dual I2C-talk: stereo or dual 3 3 3 3
Semiconductor Group
59
TDA 6610-5
Characteristics (cont'd) VS = 12 V; TA = 25 oC Parameter Mono threshold Mono threshold Mono threshold Mono threshold Detection response Detection response Switching threshold f REF-input Switching threshold f REF-input Multiplexer clock Multiplexer clock Multiplexer clock Multiplexer clock Design-Related Data Filter output resistance Symbol V25 - V25 V26 - V26 0 0 0 0 1/4 Limit Values min. typ. max. 100 100 100 100 1/2 mV mV mV mV I2C-talk: mono I2C-talk: mono I2C-talk: mono I2C-talk: mono Unit Test Condition Test Circuit 3 3 3 3
tdet tdet
tMPX
1/4 1/2 1.5
tMPX
V V s s s s
I2C-talk: stereo or dual V25 = 1 V 3 I2C-talk: stereo or dual V25 = 1 V 3 2 2 00,C0, MPX = 1 s 00,C0, MPX = 2 s 00,C0, MPX = 4 s 00,C0, MPX = 8 s
V24L V24L tMPX tMPX tMPX tMPX
0 3.5 1.08 2.17 4.34 8.68
V21
R 25, 26
110 7
k k
f REF-input resistance R 24
Semiconductor Group
60
TDA 6610-5
Characteristics VS = 12 V; TA = 25 oC Parameter Symbol min. I2C Bus (SCL, SDA) SCL, SDA edges Rise time Fall time Shift register clock pulse SCL Frequency H-pulse width L-pulse width Start Setup time Hold time Stop Setup time Bus free time Data transfer Setup time Hold time Input SCL, SDA Input voltage Input current Output SDA (open collector) Output voltage RL = 2.5 k IQL = 3 mA Limit Values typ. max. Unit
tR tF fSCL tHIGH tLOW tSUSTA tHDSTA tSUSTO tBUF tSUDAT tHDDAT VQH VQL IQH IQL VQH VQL
0 4 4 4 4 4 4 1 1 2.4
1 300 100
s ns kHz s s s s s s s s
5.5 1 20 20
V V A A V V
5.4 0.4
Semiconductor Group
61
TDA 6610-5
Test Circuit 1 Semiconductor Group 62
TDA 6610-5
Test Circuit 2 Semiconductor Group 63
TDA 6610-5
Test Circuit 3 Semiconductor Group 64
TDA 6610-5
Application Circuit 1 Semiconductor Group 65
TDA 6610-5
Application Circuit 2 Semiconductor Group 66
TDA 6610-5
I2C Bus Timing Diagram
tSUSTA tHDSTA tHIGH tLOW tSUDAT tHDDAT tSUSTO tBUF tF tR
Setup time (start) Hold time (start) H-pulse width (clock) L-pulse width (clock) Setup time (data transfer) Hold time (data transfer) Setup time (stop) Bus free time Fall time Rise time
All times referred to VIH and VIL values.
Semiconductor Group
67

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